(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming dual damascene interconnect structures in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Damascene interconnects are used in the art as an alternative to metal etched contacts. The key to damascene technology is the definition of via and trace trenches in the dielectric material. Once the trenches are defined, the metal material is deposited to fill the trenches. A polishing down process is performed to remove excess metal and complete the definition of the damascene interconnects.
FIG. 1 illustrates an integrated circuit device of the prior art. A semiconductor substrate 10 is shown. An insulating layer 14 is formed overlying the semiconductor substrate 10. Metal traces 18 are shown formed in the insulating layer 14. The metal traces 18 comprise a lower level of interconnection. A cap layer 22 overlies the metal traces 18. A first dielectric layer 26 overlies the cap layer 22. An etch stop layer 30 overlies the first dielectric layer 26. A second dielectric layer 34 overlies the etch stop layer 30.
A dual damascene interconnect will be formed in this integrated circuit device. In a dual damascene structure, trenches are etched into the dielectric material to form a via to the underlying interconnect level and to form another interconnect level. A first photoresist layer 38 is deposited overlying the second dielectric layer 34. The first photoresist layer 38 is patterned by a typical photolithographic technique to form openings where the via trenches will be formed. In this photolithographic technique, the first photoresist layer 38 is exposed to light through a mask and then is developed to remove parts of the photoresist material. The openings formed overlie at least a part of the metal traces 18 as shown.
Referring now to FIG. 2, the via trenches are etched through the second dielectric layer 34, the etch stop layer 30 and the first dielectric layer 26. The first photoresist layer 38 is used as a mask for the etch. Following the via trench etch, the first photoresist layer 38 is stripped away.
Referring now to FIG. 3, a second photoresist layer 42 is deposited overlying the second dielectric layer 34 and filling the via trench. The second photoresist layer 42 is then patterned by a typical photolithographic technique to form openings where the upper interconnect trenches will be formed. In this photolithographic technique, the second photoresist layer 42 is exposed to light through a mask and then is developed to remove parts of the photoresist material. The openings formed overlie at least a part of the via trench openings.
The upper interconnect trenches are then etched through the second dielectric layer 34 stopping at the etch stop layer 30. After the upper interconnect trenches are etched, the second photoresist layer 42 is stripped away.
Referring now to FIG. 4, the cap layer 22 is etched through to expose the metal traces 18. A metal layer 46 is deposited overlying the second dielectric layer 34 and filling the trenches. Finally, a chemical mechanical polish is performed to remove the excess metal layer 46 overlying the second dielectric layer 34 so that the metal is confined to the trenches. This completes the dual damascene structure.
Note that two complete photolithographic sequences are required to form the trenches for the dual damascene structure. In each sequence, photoresist is applied, exposed, developed, used as a mask for an etching operation, and then stripped away. If a process sequence could be devised to eliminate a step of application, exposure, developing, or stripping, then significant cost savings may result.
Several prior art approaches disclose methods to form photoresist patterns in the fabrication of dual damascene structures. U.S. Pat. No. 5,821,169 to Nguyen et al discloses a process to make dual damascene structures where a multilevel photoresist pattern is used with a hard mask layer to create multiple levels in the dielectric. U.S. Pat. No. 5,877,076 to Dai teaches a process to form a dual damascene structure where chemical amplification resist (CAR) photoresist is used. Negative and positive photoresist layers are used. The dual damascene pattern is formed in the photoresist layers and then transferred to the dielectric layers underlying by an etching process. U.S. Pat. No. 5,882,996 to Dai discloses a dual damascene process where an anti-reflective coating is used between two chemical amplification resist (CAR) layers. The dual damascene pattern is formed in the photoresist stack and transferred to the dielectric layers underlying by etching. U.S. Pat. No. 5,635,423 to Huang et al discloses a process to create dual damascene structures using two photoresist layers, exposures, develops, and strips. U.S. Pat. No. 5,741,626 to Jain et al teaches a dual damascene process where anti-reflective coating layers of Ta3N5 are used between dielectrics. U.S. Pat. No. 5,877,075 to Dai et al teaches a dual damascene process using only one photoresist to form the pattern. A CAR photoresist is used. A silylation process is used to create a temporary hard mask in a portion of the photoresist.
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating dual damascene interconnects in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate dual damascene interconnects where two photoresist patterns, used to mask the trench etches, are formed using a single develop step.
Another further object of the present invention is to provide a method to fabricate dual damascene interconnects where two photoresist patterns are formed prior to etching either trench.
In accordance with the objects of this invention, a new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The first photoresist layer is exposed, but not developed, to define patterns where via trenches are planned. A second photoresist layer is deposited overlying the first photoresist layer. The second photoresist layer is exposed to define patterns where interconnect trenches are planned. The second photoresist layer and the first photoresist layer are developed to complete the via trench pattern of the first photoresist layer and the interconnect trench pattern of the second photoresist layer. The dielectric layer is etched through where defined by the via trench pattern of the first photoresist layer. The dielectric layer is etched where defined by the interconnect pattern of the second photoresist layer, and the dual damascene interconnect of the integrated circuit device is completed.
Also in accordance with the objects of this invention, a new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The first photoresist layer is exposed and developed to define patterns where via trenches are planned. A second photoresist layer is deposited overlying the first photoresist layer and filling the openings in the via trench pattern. The second photoresist layer is exposed and developed to define patterns where interconnect trenches are planned. The dielectric layer is etched through where defined by the via trench pattern of the first photoresist layer. The dielectric layer is etched where defined by the interconnect pattern of the second photoresist layer, and the dual damascene interconnect of the integrated circuit device is completed.
Also in accordance with the objects of this invention, a new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The first photoresist layer is exposed, but not developed, to define patterns where via trenches are planned. A buffer layer is deposited overlying the first photoresist layer. A second photoresist layer is deposited overlying the buffer layer. The second photoresist layer is exposed to define patterns where interconnect trenches are planned. The second photoresist layer and the first photoresist layer are developed and the buffer layer is stripped to complete the via trench pattern of the first photoresist layer and the interconnect trench pattern of the second photoresist layer and the buffer layer. The dielectric layer is etched through where defined by the via trench pattern of the first photoresist layer. The dielectric layer is etched where defined by the interconnect pattern of the second photoresist layer and the buffer layer, and the dual damascene interconnect of the integrated circuit device is completed.